User
Sr.
Instruction
Address
Symbol
Description
1.
Normally open(NO)
I:0/0
This instruction (also called "examine
on" or "normally opened") functions as an input or storage bit.
2.
Normally Closed(NC)
I:0/0
This instruction (also called "examine
off" or "normally closed") functions as an input or storage bit
3.
Output(OTE)
O:0/0
It is used an output
4.
Output Latch(OTL)
O:0/0
Once an OTL bit has been set "on" (1 in
the memory) it will remain "on" even if the rung condition goes
false.
5.
Output Unlatch
(OUT)
O:0/0
This output instruction is used to unlatch (reset)
a latched (set) bit which was set by an OTL instruction. It is also used as reset
6.
New rung
To insert a new rung.
7.
Parallel
To insert parallel path in same rung
BIT
1.
One Shot Rising
B3:0/0
This instruction is a conditional input
instruction that triggers an event to occur one time.
Timer/Counter
1.
Timer On-Delay (TON)
T4:0
Timer will
start when its rung goes true and it will generate Done bit when
accumulated value reaches the preset value . this Done bit is used to turn ON
or OFF the Output
2.
TOF [Timer Off Delay]
T4:0
Use the TOF instruction to turn an output on or off
after its rung has been off for a preset time interval. The TOF instruction
begins to count timebase intervals when the rung makes a true-to-false
transition
3.
Retentive Timer On-Delay (RTO)
T4:0
An RTO function the same as a TON with the exception that once it has begun timing, it
holds its count of time even if the rung goes false. When rung continuity
returns (rung goes true again), the RTO begins timing from the accumulated time
which was held when rung continuity was lost.
4.
Count Up (CTU)
C5:0
This output instruction counts up for each
false-to-true transition of conditions (Whenever you switch on counter
increases )preceding it in the rung and produces an output when the accumulated
value reaches the preset value. Rung transitions might be triggered by a limit
switch or by parts traveling past a detector
5.
Count Down (CTD)
C5:0
This output instruction counts down for each
false-to-true transition of conditions preceding it in the rung and produces an
output when the accumulated value reaches the preset value. Rung transitions
might be triggered by a limit switch or by parts traveling past a detector.
6.
RESET
(RES)
Ex:-
The RESET
instruction is used to reset timers and counters. When conditions
preceding it in the rung are true, the RES resets the accumulated value and
control bits of the timer or counter. The timer or counter being controlled by
the reset instruction has the same address as the reset instruction
Compare
1.
Limit Test(LIM)
N7:0:-Low limit
If the
Low Limit has a value equal to or less than the High Limit, the instruction is
true when the Test value is between the limits or is equal to either limit. If
the Test value is outside the limits, the instruction is false.
If the
Low Limit has a value greater than the High Limit, the instruction is false
when the Test value is between the limits. If the Test value is equal to either
limit or outside the limits, the instruction is true.
2.
Equal
(EQU)
N7:0
When the Source A is equal to Source B output is
generated
3.
Not Equal
(NEQ)
N7:0
When the Source A is not equal to Source B
output is generated
4.
Less Than
(LES)
N7:0
If the value at Source A is less than the value at
Source B, the instruction is logically true.
5.
Greater
Than (GRT)
N7:0
If the value at Source A is greater than the value
at Source B, the instruction is logically true.
6.
Greater
Than or Equal To(GEQ)
N7:0
If the value at Source A is greater than or equal
to the value at Source B, the instruction is logically true
7.
Less Than
or Equal (LEQ)
N7:0
This conditional input instruction tests whether
one value (source A) is less than or equal to another (source B). If the value
at source A is less than or equal to the value at source B, the instruction is
logically true
Compute/Math
1.
Addition
Source A:-N7:0
When
rung conditions are true, this output instruction ADDS Source A to Source B and stores the result at
the destination address. Source A and Source B can either be values or
addresses that contain values, however Source A and Source B cannot both be
constants.
2.
Subtraction (SUB)
Source A:-N7:0
When rung conditions are true, the SUB output
instruction subtracts Source B from Source A and stores the result in the
destination. Source A and Source B can either be values or addresses that
contain values, however Source A and Source B cannot both be constants.
3.
Multiply(MUL)
Source A:-N7:0
Use the MUL instruction to multiply one value
(source A) by another (source B) and place the result in the destination.
Source A and Source B can either be constant values or addresses that contain values, however Source
A and Source B cannot both be constants.
4.
DIV [Divide]
Source A:-N7:0
When rung conditions are true, this output
instruction divides Source A by Source B and stores the result in the
destination and the math register. The value stored in the destination is
rounded. The value stored in the math register consists of the unrounded
quotient (placed in the most significant word) and the remainder (placed in the
least significant word).
Source A and Source B can either be constant values or addresses that contain values, however Source A and Source B cannot
both be constants.
5.
Square Root (SQR)
Source A:-N7:0
When rung conditions are true, this output
instruction calculates the square root of the absolute value of the source and
places the rounded result in the destination.
6.
Negate(NEG)
Source A:-N7:0
When rung conditions are true, the NEG instruction
changes the sign of the source and places it in the destination. The source and
destination parameters must be word addresses.
Program Control
1.
Jump to Label(JMP)
Q2:0/0
When the rung condition for this output instruction
is true, the processor jumps forward or backward to the corresponding label
instruction(LBL) and resumes program execution at the label and the rung
and there output between the jump and
label will remain same and they will not be changed until the rung condition of
jump goes false
3.
Master Control Reset(MCR)
No Address
MCR controlled areas must contain only two MCR
instructions - one to define the start and one to define the end. The rung
between this two MCR will be true only when the rung of start MCR will be true.
Other rungs which are not between this two MCR will not be affected by this MCR
4.
Subroutine
(SBR)
No address
Subroutine is used to run two or more ladders
together.Placed
as the first instruction
in a subroutine file, the SBR instruction identifies the file. This is the file number that is used in the JSR instruction to identify the target to which the
program should jump.
5.
Jump to Subroutine
(JSR)
Address of another ladder which you want to activate
JSR is used to activate another ladder. When rung conditions are true for this output
instruction, it causes the processor to jump to the targeted subroutine file.
You can only jump to the first instruction in a subroutine.
6.
Return
from Subroutine
(RET )
No address
Ret is used to end the program otherwise second
ladder will not run.This
output instruction marks the end of subroutine execution or the end of the
subroutine file. It causes the processor to resume execution in the main
program file at the instruction following the JSR instruction where it exited the program.
File Shift/Sequencer
1.
Bit Shift Left (BSL)
File :- On which BIT you have to Transfer this BIT “#B3:0”
Control:-Register address with
the help of whom you have to transfer bit“R6:0”
Bit Address:- which BIT you have to Transfer write his address “B3:1/0”
When the rung goes from false-to-true, the
processor sets the enable bit (EN bit 15) and the data block is shifted to the
left (to a higher bit number) one bit position. The specified bit at the bit
address is shifted into the first bit position.
2.
Bit Shift Right (BSR)
File :- On which BIT you have to Transfer this BIT
Control:-Register address with
the help of whom you have to transfer bit
Bit Address:- which BIT you have to Transfer write his address
When the rung goes from false-to-true, the enable
bit (EN bit 15) is set and the data block is shifted to the right (to a lower
bit number) one bit position. The specified bit at the bit address is shifted
into the last bit position. The first bit is shifted out of the array and
stored in the unload bit (UL bit 10) in the status byte of the control element
User
Sr.
no.
|
Instruction
|
Address
|
Symbol
|
Description
|
1.
|
Normally open(NO)
|
I:0/0
|
|
This instruction (also called "examine
on" or "normally opened") functions as an input or storage bit.
|
2.
|
Normally Closed(NC)
|
I:0/0
|
|
This instruction (also called "examine
off" or "normally closed") functions as an input or storage bit
|
3.
|
Output(OTE)
|
O:0/0
|
|
It is used an output
|
4.
|
Output Latch(OTL)
|
O:0/0
|
|
Once an OTL bit has been set "on" (1 in
the memory) it will remain "on" even if the rung condition goes
false.
|
5.
|
Output Unlatch
(OUT) |
O:0/0
|
|
This output instruction is used to unlatch (reset)
a latched (set) bit which was set by an OTL instruction. It is also used as reset
|
6.
|
New rung
|
|
To insert a new rung.
|
|
7.
|
Parallel
|
|
To insert parallel path in same rung
|
BIT
1.
|
One Shot Rising
(OSR)
|
B3:0/0
|
This instruction is a conditional input
instruction that triggers an event to occur one time.
|
Timer/Counter
1.
|
Timer On-Delay (TON)
|
T4:0
|
|
Timer will
start when its rung goes true and it will generate Done bit when
accumulated value reaches the preset value . this Done bit is used to turn ON
or OFF the Output
|
2.
|
TOF [Timer Off Delay]
|
T4:0
|
|
Use the TOF instruction to turn an output on or off
after its rung has been off for a preset time interval. The TOF instruction
begins to count timebase intervals when the rung makes a true-to-false
transition
|
3.
|
Retentive Timer On-Delay (RTO)
|
T4:0
|
|
An RTO function the same as a TON with the exception that once it has begun timing, it
holds its count of time even if the rung goes false. When rung continuity
returns (rung goes true again), the RTO begins timing from the accumulated time
which was held when rung continuity was lost.
|
4.
|
Count Up (CTU)
|
C5:0
|
|
This output instruction counts up for each
false-to-true transition of conditions (Whenever you switch on counter
increases )preceding it in the rung and produces an output when the accumulated
value reaches the preset value. Rung transitions might be triggered by a limit
switch or by parts traveling past a detector
|
5.
|
Count Down (CTD)
|
C5:0
|
|
This output instruction counts down for each
false-to-true transition of conditions preceding it in the rung and produces an
output when the accumulated value reaches the preset value. Rung transitions
might be triggered by a limit switch or by parts traveling past a detector.
|
6.
|
RESET
(RES) |
Ex:-
TIMER
T4:0
COUNTER
C5:0
|
|
The RESET
instruction is used to reset timers and counters. When conditions
preceding it in the rung are true, the RES resets the accumulated value and
control bits of the timer or counter. The timer or counter being controlled by
the reset instruction has the same address as the reset instruction
|
Compare
1.
|
Limit Test(LIM)
|
N7:0:-Low limit
N7:1:-Test
N7:2:-High limit
|
|
If the
Low Limit has a value equal to or less than the High Limit, the instruction is
true when the Test value is between the limits or is equal to either limit. If
the Test value is outside the limits, the instruction is false.
If the
Low Limit has a value greater than the High Limit, the instruction is false
when the Test value is between the limits. If the Test value is equal to either
limit or outside the limits, the instruction is true.
|
2.
|
Equal
(EQU) |
N7:0
|
|
When the Source A is equal to Source B output is
generated
|
3.
|
Not Equal
(NEQ)
|
N7:0
|
|
When the Source A is not equal to Source B
output is generated
|
4.
|
Less Than
(LES)
|
N7:0
|
|
If the value at Source A is less than the value at
Source B, the instruction is logically true.
|
5.
|
Greater
Than (GRT)
|
N7:0
|
|
If the value at Source A is greater than the value
at Source B, the instruction is logically true.
|
6.
|
Greater
Than or Equal To(GEQ)
|
N7:0
|
| If the value at Source A is greater than or equal to the value at Source B, the instruction is logically true |
7.
|
Less Than
or Equal (LEQ)
|
N7:0
|
|
This conditional input instruction tests whether
one value (source A) is less than or equal to another (source B). If the value
at source A is less than or equal to the value at source B, the instruction is
logically true
|
Compute/Math
1.
|
Addition
(ADD)
|
Source A:-N7:0
Source B:-
N7:1
Dest:-
N7:2
|
|
When
rung conditions are true, this output instruction ADDS Source A to Source B and stores the result at
the destination address. Source A and Source B can either be values or
addresses that contain values, however Source A and Source B cannot both be
constants.
|
2.
|
Subtraction (SUB)
|
Source A:-N7:0
Source B:-
N7:1
Dest:-
N7:2
|
|
When rung conditions are true, the SUB output
instruction subtracts Source B from Source A and stores the result in the
destination. Source A and Source B can either be values or addresses that
contain values, however Source A and Source B cannot both be constants.
|
3.
|
Multiply(MUL)
|
Source A:-N7:0
Source B:-
N7:1
Dest:-
N7:2
|
|
Use the MUL instruction to multiply one value
(source A) by another (source B) and place the result in the destination.
Source A and Source B can either be constant values or addresses that contain values, however Source
A and Source B cannot both be constants.
|
4.
|
DIV [Divide]
|
Source A:-N7:0
Source B:-
N7:1
Dest:-
N7:2
|
|
When rung conditions are true, this output
instruction divides Source A by Source B and stores the result in the
destination and the math register. The value stored in the destination is
rounded. The value stored in the math register consists of the unrounded
quotient (placed in the most significant word) and the remainder (placed in the
least significant word).
Source A and Source B can either be constant values or addresses that contain values, however Source A and Source B cannot
both be constants.
|
5.
|
Square Root (SQR)
|
Source A:-N7:0
Dest:-
N7:2
|
|
When rung conditions are true, this output
instruction calculates the square root of the absolute value of the source and
places the rounded result in the destination.
|
6.
|
Negate(NEG)
|
Source A:-N7:0
Dest:-
N7:2
|
|
When rung conditions are true, the NEG instruction
changes the sign of the source and places it in the destination. The source and
destination parameters must be word addresses.
|
Program Control
1.
|
Jump to Label(JMP)
|
Q2:0/0
|
|
When the rung condition for this output instruction
is true, the processor jumps forward or backward to the corresponding label
instruction(LBL) and resumes program execution at the label and the rung
and there output between the jump and
label will remain same and they will not be changed until the rung condition of
jump goes false
|
3.
|
Master Control Reset(MCR)
|
No Address
|
|
MCR controlled areas must contain only two MCR
instructions - one to define the start and one to define the end. The rung
between this two MCR will be true only when the rung of start MCR will be true.
Other rungs which are not between this two MCR will not be affected by this MCR
|
4.
|
Subroutine
(SBR) |
No address
|
|
Subroutine is used to run two or more ladders
together.Placed
as the first instruction
in a subroutine file, the SBR instruction identifies the file. This is the file number that is used in the JSR instruction to identify the target to which the
program should jump.
|
5.
|
Jump to Subroutine
(JSR) |
Address of another ladder which you want to activate
|
|
JSR is used to activate another ladder. When rung conditions are true for this output
instruction, it causes the processor to jump to the targeted subroutine file.
You can only jump to the first instruction in a subroutine.
|
6.
|
Return
from Subroutine
(RET ) |
No address
|
|
Ret is used to end the program otherwise second
ladder will not run.This
output instruction marks the end of subroutine execution or the end of the
subroutine file. It causes the processor to resume execution in the main
program file at the instruction following the JSR instruction where it exited the program.
|
File Shift/Sequencer
1.
|
Bit Shift Left (BSL)
|
File :- On which BIT you have to Transfer this BIT “#B3:0”
Control:-Register address with the help of whom you have to transfer bit“R6:0”
Bit Address:- which BIT you have to Transfer write his address “B3:1/0”
|
|
When the rung goes from false-to-true, the
processor sets the enable bit (EN bit 15) and the data block is shifted to the
left (to a higher bit number) one bit position. The specified bit at the bit
address is shifted into the first bit position.
The last bit is shifted out of the array and stored in
the unload bit (UL bit 10). |
2.
|
Bit Shift Right (BSR)
|
File :- On which BIT you have to Transfer this BIT
Control:-Register address with
the help of whom you have to transfer bit
Bit Address:- which BIT you have to Transfer write his address |
|
When the rung goes from false-to-true, the enable
bit (EN bit 15) is set and the data block is shifted to the right (to a lower
bit number) one bit position. The specified bit at the bit address is shifted
into the last bit position. The first bit is shifted out of the array and
stored in the unload bit (UL bit 10) in the status byte of the control element
|
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